Lattice Radiant software is a full featured FPGA design tool suite that enables predictable design convergence with unmatched ease-of-use. Embracing our corporate mission of enabling edge connectivity and computing designs, the Radiant software was specifically created for the development of edge applications. The Radiant software was architected from the ground up to enable a predictable design convergence with its complete unified design framework. This includes a unified database containing all design implementation steps, a set of consistent design constraints, as well as a unified timing analysis engine, which is used throughout the entire design implementation flow. It also supports industry standard Synopsys Design Constraint (SDC) for maximum interoperability, as well as the latest industry standard IEEE1735 IP encryption which enriches customer’s IP ecosystem support. Radiant software aims to enable broad market low power embedded applications with the Lattice iCE40 UltraPlus devices, the world’s smallest FPGAs with enhanced memory and DSPs to enable always on, distributed processing for IoT edge applications. The software also comes pre-loaded with the necessary IPs to design for such applications. Designed specifically to enable designers to quickly build energy-efficient solutions that meet the processing demands of next-generation Internet of Things (IoT), industrial and automotive products, iCE40 UltraPlus devices have extensive FPGA fabric for custom logic, large amounts of low power non-volatile configuration memory for instant-on applications, and up to 8 multiply/accumulate blocks for signal processing. User experience is another strong focus of Radiant software. Radiant features a redesigned user interface, which is simple, intuitive and efficient in every aspect of the operation. A new start page provides a simple entry point to user’s project. In terms of design constraint management, there are timing constraint editor and device constraint editor tools for convenient editing and viewing of all the logical and physical design limitations of user’s design. The integrated toolset environment within Radiant software significantly improves ease of design navigation and debugging, and includes a common messaging window with advanced filtering capabilities. Finally, the “one-click” design implementation simplifies operation by integrating execution, process toolbar, and the corresponding implementation report into a single window, bringing the overall ease of use to a whole new level. Other productivity-improving features of Radiant software include the complete close-loop physical to logic design implementation cross probing capability, a silicon data-driven power calculator for accurate power analysis and estimation tool, as well as an industry competitive Reveal Hardware Debugger logic analyzer tool – will help to enable faster overall FPGA design closure. Additionally, Lattice recently announced the availability of the latest version of Lattice Radiant software, version 2.0. When system developers evaluate hardware platforms, the actual hardware is only a part of their selection criteria. They also evaluate the design software used to configure the hardware for its ease-of-use and supported features, as these features can have a significant impact on overall system development time and cost. Lattice Radiant 2.0 design software gives developers an easy-to-follow user experience; the tool leads them through the design flow from design creation, to importing IP, to implementation, to bitstream generation, to downloading the bitstream onto an FPGA. Developers with little to no experience working with FPGAs should be able to quickly leverage the automated features of Lattice Radiant. For experienced FPGA developers, Lattice Radiant 2.0 allows for more granular control over FPGA settings if specific optimizations are required. New feature upgrades available in Radiant 2.0 include: – An on-chip debugging tool that allows users to conduct bug fixes in real time. The debugging feature lets developers insert virtual switches or LEDs in their code to confirm viability. The tool also lets users change hard IP block settings to test different operating modes. – Improved timing analysis provides more accurate trace and route planning and clock timing to avoid design congestion and thermal issues. – The engineering change order (ECO) editor lets developers make incremental changes to a completed design without having to recompile the entire FPGA database. – The Simultaneous Switching Output (SSO) calculator analyzes the signal integrity of individual pins to ensure their performance isn’t adversely affected by their proximity to another pin., Interest across markets in leveraging AI and machine learning (AI/ML) is increasing and there is also a large demand for low power high-tech devices with AI/ML processing capabilities to operate at the network Edge. Advanced processing at the Edge is important to reduce latency to end points and end users, and to maintain better user privacy. In addition, intelligent Edge devices filter data traffic to the cloud, reducing network costs and bandwidth. Many of these intelligent Edge devices use image sensors to support various embedded vision applications and include AI/ML-driven applications such as object counting or presence detection.