Company: Introspect Technology
Category: Engineering Development/Design Tool of the Year
The SV4E-I3C is an all-inclusive solution for I3C-based interface development, test, and programming. It gives developers unprecedented opportunities to craft innovative designs for any electronic product that requires sensing and control – from smartphones, to wearables, to systems in automobiles and data centers. Containing three instruments in one, this tool can act as a protocol exerciser for validating and debugging I3C slave or master devices. It can also act as a complete protocol analyzer with fine-resolution timing analysis and a full suite of conformance test capability. Finally, it contains a deep vector memory, which allows it to be used as a general purpose I3C device programmer. All three categories of instrumentation features are accessible simultaneously and in real-time using the award winning Introspect ESP Software.
The I3C standard was originally developed by MIPI® Alliance, and it is a scalable, medium-speed, control bus interface for connecting peripherals to an application processor or host controller. With its recent adoption by JEDEC® for the DDR5 ecosystem, the I3C standard is now rapidly becoming the specification of choice for applications that traditionally depended on I2C or SPI interfaces. For example, power management ICs (PMIC), thermal sensors, control hubs, and many other peripherals can benefit from this new standard to enable much richer user experiences and much faster data transfer speeds. Therefore, the SV4E-I3C has a far-reaching impact across multiple industries.
Innovation and Outstanding Performance
Having a truly compact design with dimensions of only 140 mm x 189 mm, the SV4E-I3C packs unique technologies that make it unlike any other solution in its category. On the one hand, it integrates four internal I3C device emulators that can act as either a master, slave, or both, thus providing the richest functional validation coverage. And, on the other hand, it supports full analog coverage and speedy automated execution that make it akin to Automated Test Equipment (ATE). This combination leads to much easier deployment in any desktop context. In short, engineers can have their own ATE-on-bench setup from the comfort of their home or work office.
The SV4E-I3C also includes multiprotocol support, with a specific focus on I3C, I3C Basic, JESD403-1 (SidebandBus), and JEDEC device support. With the JESD403-1 and JEDEC device support, the SV4E-I3C provides features for individually exercising devices related to the DDR5 ecosystem such as PMIC, SPD Hub, and TS. With its deep vector memory, it also provides features for controlling and analyzing a fully populated memory module such as an R-DIMM. For example, a single SV4E-I3C can instantiate multiple master and slave devices internally, thus providing an ideal self-contained solution for completely characterizing an SPD Hub. In this setup, a master instance from the SV4E-I3C can drive the SPD Hub as if the SV4E-I3C is a main SidebandBus Host Controller on a server. Then, a slave instance on the SV4E-I3C can be connected to the other side of the hub and act as a PMIC or Thermal Sensor. Such end-to-end capability ensures complete design and fault coverage during all stages of product development: from early prototypes to system-level regression and high volume manufacturing.
For DIMM testing, the SV4E-I3C offers a highly intuitive SidebandBus Controller programming interface that can automatically initialize a bus, enumerate devices on the bus, and automatically discover capabilities of connected devices on the bus. This makes it ideal for regression testing, burn-in testing, or mass production testing of fully-populated DIMMs.
Finally, the SV4E-I3C contains an inventive real-time oscilloscope feature that can allow it to capture instantaneous events and glitches on the data and clock lines of the I3C bus. This adds to its “all-inclusive” nature and eliminates the need for extremely expensive oscilloscopes (costing tens of thousands of dollars) during design validation and debug stages. This feature alone represents a tremendous advancement in the field of digital design debug and validation for I3C and control bus implementations.
Impact on the Market
With an ability to generate compliant and non-compliant traffic, as well as an ability to operate in both slave and master modes, the SV4E-I3C enables seamless validation of any MIPI I3C or JESD403-1 device. This broad reach has made the SV4E-I3C indispensable as a tool for design engineers, validation engineers, and software engineers focused on creating sensor or control components. Specifically, because the I3C technology is so new, engineers are hungry for reference tools to help ensure interoperability in real-world circumstances. So, the SV4E-I3C’s introduction to the market has been extremely timely for enabling adoption of the I3C standards.
With Introspect Technology’s constant tracking of specification roadmaps, the SV4E-I3C enables companies to remain well ahead of the curve when it comes to MIPI and JEDEC specifications evolution. For example, the product was created with the first MIPI I3C Version 1.0 specification, and it has since evolved to include Version 1.1 and I3C Basic Version 1.0. It has also included JEDEC specification support. Indeed, developed in lock-step with some of the most advanced CPU and memory chip makers in the world, the SV4E-I3C is constantly supporting the latest protocol nuances. It is, therefore, with little surprise that it is finding rapid adoption in the marketplace.
Webinars and Video Channels
Introduction to I3C: https://register.gotowebinar.com/register/8766219688391017985
Interoperability Webinar: https://www.mipi.org/devcon/2020/agenda/interoperability-challenges-and-solutions-mipi-i3c
Youtube Channel: https://youtube.com/playlist?list=PLdH_GRdVEPYO3QxV_EJg2Y3v3538ygqzg