The SV5C Personalized SerDes Tester is a 16-channel parallel bit error rate tester that is particularly optimized for characterizing and exercising DDR5 memory components and controllers as defined by the JEDEC Industry Association. The DDR5 standard, which is not released to the market yet, is the memory interface solution for next-generation server technology, and it is fundamental to the deployment of new 5G and Artificial Intelligence (AI) architectures into the data center.

The SV5C Personalized SerDes Tester enables exercising and characterizing JEDEC DDR5 designs, with specific strength in the domain of receiver stress testing. Because of the high transfer speeds and advanced equalization algorithms in DDR5, receiver sensitivity testing is critical for the successful deployment of high-speed DDR5 applications, and the SV5C facilitates this process with remarkable ease. Capable of generating any protocol traffic such as host-controller training sequences, this compact instrument includes precision analog parameter controls that allow users to gain deep characterization insights into receiver sensitivity performance and dynamic skew or jitter tolerance. It also contains a full suite of transmitter test capability, and it is the only instrument in the world that can provide host-emulation to test memory devices or memory emulation to test host controllers.

Innovation and Outstanding Performance
What makes the SV5C unlike any other product in the test and measurement marketplace is that the SV5C is a new hybrid tool: it provides massively parallel lane-count coverage, as well as highly-automated and speedy test execution akin to production Automatic Test Equipment (ATE) – all while simultaneously offering superior analog performance that rivals conventional high-end (and high-cost) analog tools typically deployed for only single-lane characterization. All of these capabilities come in a handheld form factor, which means that engineers can deploy an entire validation bench within a compact box that travels inside any briefcase. A compact solution translates into easier deployment in an already crammed and often resource‐constrained lab. It also means that engineers can have their own “high performance” bench right at their desk without needing to go to the “ATE lab”.

With its compactness, ease of setup, extreme analog performance, and fully integrated jitter and skew injection sources, the SV5C has increased the availability of world‐class equipment and ease of use for high‐speed digital product development teams across the world. To quantify this, a single SV5C instrument contains 16 independent skew and jitter injection channels that can operate in parallel and that are completely programmable through software — they do not require external hardware. By contrast, a conventional Bit Error Rate Tester (BERT), the typical tool used for receiver jitter testing on JEDEC buses, only supports 1 or 2 jitter injection channels, takes up more space in the lab, and costs significantly more than the SV5C. Similarly, the SV5C automatically calibrates timings between its channels, thus requiring virtually no laboratory setup time, whereas conventional tools can take hours to prepare in advance of testing. Finally, the SV5C incorporates an innovative pattern timeline architecture (see accompanying video here: that can generate very complex pattern sequences representing hundreds of thousands of transactions between a memory controller and a DDR5 memory — a typical instrument would struggle to achieve this because it requires storing long and fixed patterns in its finite digital vector storage space. The SV5C’s pattern timeline architecture can generate all of these transactions in real-time while simultaneously injecting jitter and measuring device responses. The ability to generate large sequences is critical for covering the millions of operating combinations that DDR5 developers must grapple with when designing and validating their systems.

Through an open-source Python software scripting environment, the SV5C can be used to transmit JEDEC-compliant data packets with a multitude of digital formats across complete communications links (command, address, and data buses), inject both physical-layer and protocol-layer impairments for stress testing, and interoperate with a myriad of devices. Because of this flexibility, this instrument is not only finding wide-spread usage in characterization labs, but it is also being deployed in pre-Silicon design validation activities as well as in Hardware in the Loop (HIL) simulation environments. These varied deployment models are true testimony to the flexibility of this “category-creating” tool. Simply stated, there is no single tool that is quite like the SV5C in the current memory interface test marketplace.

A Webinar describing the SV5C and its application to DDR5 testing is included here:

Impact on the Market
Created to support the CPU makers, the DRAM memory chip makers, the data buffer and register/control device makers, and the memory module makers, the SV5C is the only tool in the industry that offers the capability to understand the global operating limits of JEDEC memory interface devices and also measure their real-world analog performance. By supporting a compliant physical layer and unique protocol layers, a single SV5C can be deployed to multiple device characterization programs, thus enabling users to support multiple product development roadmaps with a single instrument. For example, a CPU maker and a DRAM memory chip maker can both use the single instrument to ensure interoperability and significantly accelerate their joint time to market.

With the SV5C, companies can remain well ahead of the curve when it comes to JEDEC specifications evolution. For example, memory technology currently reaches 3.2 Gbps per pin, whereas the SV5C supports 12.5 Gbps per pin. This means that even as DDR5 starts to move to 6.4 Gbps and then 8 Gbps, the same SV5C will be completely compatible with all of these future iterations of the standard. Additionally, the SV5C is designed to address the entire memory interface marketplace within its compact form factor, and this means that it contains I3C host controller interfaces for testing Power Management Integrated Circuits (PMIC), hub devices, and sideband bus devices. Indeed, developed in lock-step with some of the most advanced CPU and memory chip makers in the world, the SV5C is constantly supporting the latest protocol nuances. It is, therefore, with little surprise that the SV5C is rapidly becoming standard fare in any high-speed lab in which DDR5 development and characterization is being performed.

MK D014E E 20063 SV5C Data Sheet

SV5C Press Release

DDR5 Press Release

DDR5 Webinar

Solutions for DDR5 Interfaces